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61	Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms Samuel Williams∗†, Leonid Oliker∗, Richard Vuduc§, John Shalf∗, Katherine Yelick∗†, James Demmel† ∗ CRD/NERSC, Lawrenc Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-07 00:12:17 Computer memory Cache Computer architecture Compiler optimizations CPU cache Central processing unit Opteron Cell Sparse matrix-vector multiplication Loop nest optimization Multi-core processor Advanced Micro Devices
62	RDMA with PMEM Software mechanisms for enabling access to remote persistent memory Chet Douglas Intel Corporation Add to Reading List Source URL: www.snia.org Language: English - Date: 2015-09-25 15:39:02 Computer memory Remote direct memory access Persistent memory CPU cache Cache ISCSI Extensions for RDMA
63	1 Optimal Tile Size Selection Guided by Analytical Models∗ Basilio B. Fraguelaa , Mart´ın G. Carmuejaa , Diego Andradea a Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2005-09-23 06:13:05 Cache Computer architecture Computer memory Central processing unit CPU cache Optimizing compiler Memory hierarchy Genetic algorithm Program optimization Algorithm Itanium Cache-oblivious algorithm
64	IBM T. J. Watson Research Center Evaluation of Blue Gene/Q HTM Joint work with Amy Wang, Matthew Gaudet, Peng Wu, Martin Ohmacht, Jose Amaral, Christopher Barton, Raul Silvera Add to Reading List Source URL: rp-www.cs.usyd.edu.au Language: English Computer memory Cache Computer architecture CPU cache Central processing unit Parallel computing Blue Gene Speculative
65	Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-09-26 05:52:30 Cache coherency MESI protocol Cache coherence Cache False sharing Multiprocessing Draft:Cache memory CPU cache
66	New Results on Web Caching with Request Reordering Susanne Albers Abstract We study web caching with request reordering. The goal is to maintain a cache of web documents so that a sequence of requests can be served at l Add to Reading List Source URL: www14.in.tum.de Language: English - Date: 2013-11-25 11:03:09 Cache Online algorithms Analysis of algorithms Computer architecture Algorithm Competitive analysis CPU cache
67	Design of Parallel and High Performance Computing HS 2015 Torsten Hoefler, Markus P¨ uschel Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-10-01 06:53:45 Cache coherency MESI protocol Cache False sharing Draft:Cache memory CPU cache
68	On the Performance Prediction of BLAS-based Tensor Contractions Elmar Peise, Diego Fabregat-Traver, and Paolo Bientinesi AICES, RWTH Aachen {peise,fabregat,pauldj}@aices.rwth-aachen.de Add to Reading List Source URL: www.dcs.warwick.ac.uk Language: English - Date: 2014-11-13 12:51:32 Numerical linear algebra Tensors Numerical software Basic Linear Algebra Subprograms GPGPU Cache Tensor contraction Tensor Matrix CPU cache Kernel Compute kernel
69	Cache Memories Marc Moreno Maza University of Western Ontario, London, Ontario (Canada) CS2101 October 2012 Add to Reading List Source URL: www.csd.uwo.ca Language: English - Date: 2014-11-03 23:52:18 Computer memory Computer architecture Cache CPU cache Central processing unit Draft:Cache memory Memory hierarchy
70	The Semantics of Power and ARM Multiprocessor Machine Code Jade Alglave2 Anthony Fox1 Samin Ishtiaq3 Magnus O. Myreen1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Central processing unit Computer architecture Computer memory Parallel computing Instruction set architectures Memory barrier Processor register Instruction set ARM architecture ALGOL 68 CPU cache Computer data storage

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